IEICE Transactions on Electronics
Online ISSN : 1745-1353
Print ISSN : 0916-8524
Volume E98.C, Issue 11
Displaying 1-11 of 11 articles from this issue
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  • Shoichiro KAWASHIMA, Keizo MORITA, Mitsuharu NAKAZAWA, Kazuaki YAMANE, ...
    Article type: PAPER
    Subject area: Integrated Electronics
    2015Volume E98.CIssue 11 Pages 1047-1057
    Published: November 01, 2015
    Released on J-STAGE: November 01, 2015
    JOURNAL RESTRICTED ACCESS
    An 8-Mbit 0.18-µm CMOS 1T1C ferroelectric RAM (FeRAM) in a planar ferroelectric technology was developed. Even though the cell area of 2.48 µm2 is almost equal to that of a 4-Mbit stacked-capacitor FeRAM (STACK FeRAM) 2.32 µm2[1], the chip size of the developed 8-Mbit FeRAM, including extra 2-Mbit parities for the error correction code (ECC), is just 52.37 mm2, which is about 30% smaller than twice of the 4-Mbit STACK FeRAM device, 37.68mm2×2[1]. This excellent characteristic can be attributed to the large cell matrix architectures of the sectional cyclic word line (WL) that was used to increase the column numbers, and to the 1T1C bit-line GND level sensing (BGS)[2][3] circuit design intended to sense bit lines (BL) that have bit cells 1K long and a large capacitance. An access time of 52 ns and a cycle time of 77 ns in RT at a VDD of 1.8 V were achieved.
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