高力率整流回路によりキャパシタ容量を低減した並列形瞬時電圧低下補償装置

小島 鉄也; 高内 俊彦; 伊瀬 敏史; 伊与田 功; 河野 良之; 天満 耕司; 笹尾 博之; 山崎 清美; 井上 順介; 武内 保憲

doi:10.1541/ieejpes.125.5

Abstract

A new circuit of parallel type voltage sag compensator is proposed in this paper. The proposed voltage sag compensator can reduce the necessary capacity of the energy storage capacitor for compensation by boost type power factor correction rectifier charging the capacitor during a voltage sag. As a result the proposed system can reduce the size and maintenances of the apparatus.
This paper shows principle and control system of the proposed circuit. Compensation characteristics were demonstrated by simulation and experiment.

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