Timing closure in LSI design is becoming more and more difficult. But the conventional interconnect RC extraction method has over-margins caused by its corner conditions settings. In this paper, statistical corner conditions using the independence of variations between process parameters and between interconnect layers are proposed, with examinations using the measurement data. As a result of the method, the fast-to-slow guardband decreases by half in average, compared to the conventional method. The proposed method is ready for implementation to LPE tools.